An MTJ element used in a memory cell of an MRAM includes a pinned magnetic layer whose magnetization is pinned in an optional direction, and a free magnetic layer whose magnetization is variable by an external magnetic field. The pinned magnetic layer and the free magnetic layer are laminated such that a tunnel insulating film is put between them. In the MRAM, a 1-bit storage data is assigned to the relative magnetization state between the pinned magnetic layer and the free magnetic layer. For example, when the magnetizations of the pinned magnetic layer and the free magnetic layer are equal in direction, namely, parallel, the data is defined as “0”. When the magnetizations of the pinned magnetic layer and the free magnetic layer are different from each other by 180 degrees, namely, anti-parallel, the data is defined as “1”. A read operation of the MRAM is performed by using that the MTJ resistance is different depending on the magnetization state.
In order to read the MTJ resistance, it is general to apply a predetermined voltage to the MTJ element and read a sensing current (a current sensing method). However, a ratio of an MTJ resistance Rj0 in case of “0” and an MTJ resistance Rj1 in case of “1”, namely, an MR ratio is 30% to 50% at most. Thus, a read signal is not too great. In a typical MRAM, a reference cell having a middle resistance between Rj0 and Rj1 is arranged inside a memory array, and the read operation is performed. In this case, a substantial read signal is ½ of the MR ratio. Therefore, such a low MR ratio is insufficient to perform a high speed read operation of several ns. Moreover, in the current sensing method, there is a drawback that a long time is required to carry out a current-voltage conversion and that the sensing amplifier becomes large in size.
As its countermeasure, the MRAM in which the MTJ resistance is read by using a voltage is disclosed in Japanese Patent Application Disclosure (JP-P2004-220759A (hereafter, to be referred to as ['759 Application]). FIGS. 1 and 2 show a part of a configuration of the MRAM disclosed in the '759 application. FIG. 1 mainly shows a write operation, and FIG. 2 mainly shows a read operation. Here, the MRAM contains a plurality of memory cells 102, a plurality of first bit lines (/WBL) 104, a plurality of second bit lines (WBL) 105, a plurality of third bit lines (RBL) 110, a plurality of first word lines (WWL) 103a, a plurality of second word lines (RWL) 103b, a write circuit 109 and a sense amplifier 108. It should be noted that on the drawings in this Description, the MTJ elements are shown by the symbols of variable resistors.
The first word line 103a and the second word line 103b constitute a word line set and extend in an X-direction. The first bit line 104, the second bit line 105 and the third bit line 110 constitute a bit line set and extend in a Y-direction. In the first bit line 104 and the second bit line 105, their one ends are connected to the write circuit 109. In the third bit line 110, one end is connected to the sense amplifier 108. The plurality of memory cells 102 are arranged in a matrix. The plurality of memory cells 102 are arranged the intersections between the plurality of word line sets and a plurality of bit line sets. The write circuit 109 sends complementary write currents Iy and /Iy to the first bit line 104 and the second bit line 105 of a selection bit line set selected from the plurality of bit line sets based on an address signal, in a direction determined based on a write data Din, at the time of the write operation. The sense amplifier 108 compares a voltage of the third bit line 110 and a reference voltage (Vdd/2) at the time of the read operation, and outputs the comparison result as a read data Qout.
The memory cell 102 contains an MTJ element J0, a transistor M0, a transistor M1 and an MTJ element J1. The MTJ element J0, the transistor M0, the transistor M1 and the MTJ element J1 are connected in series between the first bit line 104 and the second bit line 105 in this order. The third bit line is connected to a node N1 in the middle point between the transistor M0 and the transistor M1. The transistors M0 and M1 are controlled to be turned on/off in response to a signal on the second word line 103b. The MTJ element J0 is arranged near the point at which the first bit line 104 and the first word line 103a intersect. The MTJ element J1 is arranged near the point at which the second bit line 105 and the first word line 103a intersect.
With reference to FIG. 1, in this memory cell 102, the complementary data are written into the two MTJ elements J0 and J1 connected in series. That is, in the write operation of the memory cell 102, a write current Ix is firstly sent into the first word line 103a. Moreover, the write current /Iy is sent into the first bit line 104, and the write current Iy is sent into the second bit line 105, complementarily. Here, the write current Iy and the write current /Iy always flow in the directions opposite to each other. By those write currents, the complementary data are written to the MTJ element J0 and the MTJ element J1. That is, any one state of “0” and “1” is written to the MTJ element J0, and any one state between “1” and “0” is written to the MTJ element J1.
With reference to FIG. 2, in the read operation of the memory cell 102, the second word line 103b is firstly activated to turn on the transistors M0 and M1. Then, a power supply voltage (Vdd) is applied to the second bit line 105, and a ground voltage (Gnd) is applied to the first bit line 104. Thus, a read current IR flows through the MTJ element J0 and the MTJ element J1 that are connected in series. At this time, a sense voltage Vs as a voltage at a node N1 is outputted to the third bit line 110. The sense voltage Vs has any one of the higher voltage and the lower voltage than Vdd/2 in accordance with the storage states of the MTJ elements J0 and J1. For example, when the MTJ element J0 is “0” (in the low resistance state) and the MTJ element J1 is “1” (in the high resistance state), Vs<Vdd/2. On the other hand, when the MTJ element J0 is “1” and the MTJ element J1 is “0”, Vs>Vdd/2. The merit of this memory cell 102 lies in that, since the two MTJ elements for storing the complementary data are used to carry out the read operation, the read signal is great. Moreover, since the read signal is based on a voltage (a voltage sensing method), as the sense amplifier for amplifying the signal, it is possible to use the circuit similar to the conventional DRAM. Thus, the small circuit can be used to carry out the amplification at a high speed.
However, not only in the MRAM cell noted in the '759 application but also in the typical MRAM cell, a data is written into a selection memory cell by use of a synthetic magnetic field generated based on the write current Ix and the write current Iy whose current directions are orthogonal to each other. Thus, if the current values of the write currents Ix and Iy are small, the write operation cannot be performed. Oppositely, if the current values are large, the data is erroneously written into non-selected memory cells. Thus, in order to selectively perform the write operation, the current value and the current waveform are required to be accurately controlled. Therefore, it is not easy to perform the high speed write operation.
On the other hand, the memory cell (2-Transistor—1-MTJ Memory Cell: 2T1MTJ Cell) that allows a write margin of the MRAM to be dramatically improved is disclosed in Japanese Patent Application Publication (JP-P2004-348934A) (hereinafter, to be referred to as ['934 Application]). FIGS. 3 and 4 are diagrams showing a part of the configuration of the MRAM disclosed in the '934 application. FIG. 3 mainly shows the write operation, and FIG. 4 mainly shows the read operation. Here, the MRAM contains a plurality of memory cells 202, a plurality of first bit lines (/WBL) 204, a plurality of second bit lines (WBL) 205, a plurality of third bit lines (RBL) 210, a plurality of word lines (WL) 203, a write circuit 209 and a sense amplifier 208.
The word line 203 extends in the X-direction. The first bit line 204, the second bit line 205 and the third bit line 210 constitute the bit line set and extend in the Y-direction. In the second bit line 204 and the second bit line 205, their one ends are connected to the write circuit 209. In the third bit line 210, one end is connected to the sense amplifier 208. The plurality of memory cells 202 are arranged in a matrix. The plurality of memory cells 202 are provided at the intersections of the plurality of word lines 203 and the plurality of bit line sets. The write circuit 209 sends a write current Iw to a route of the first bit line 204—the selection cell 202—the second bit line 205, in a selection bit line set selected from the plurality of bit line sets in accordance with the address signal, in a direction corresponding to the write data Din, at the time of the write operation. However, the selection memory cell 202 is selected from the plurality of memory cells 202 based on the selection bit line set and the selection word line 203 selected from the plurality of word lines 203. The sense amplifier 208 compares a read current IR flowing through the third bit line 110 and a reference current flowing through a reference bit line RBLR at the time of the read operation, and outputs the comparison result as the read data Qout.
The memory cell 202 includes a first transistor 206, a second transistor 216 and an MTJ element 207 (2T1MTJ), In the first transistor 206, its gate is connected to the word line 203, and one terminal is connected to the first bit line 204. In the second transistor 216, its gate is connected to the word line 203, one terminal is connected to the other terminal of the first transistor 206, and the other terminal is connected to the second bit line 205. That is, the first transistor 206 and the second transistor 216 are connected in series between the first bit line 204 and the second bit line 205. In the MTJ element 207, one terminal is connected to the connection point between the first transistor 206 and the second transistor 216, and the other terminal is connected to the third bit line 210.
With reference to FIG. 3, in the write operation of the memory cell 202, a decoder (not shown) selects and activates the selection word line 3 from the plurality of word lines 3, and turns on the first transistor 206 and the second transistor 216. Then, the write circuit 209 sets one of the second bit line 205 and the first bit line 204 to the power supply voltage (Vdd) and sets the other to the ground voltage (Gnd), in accordance with the write data Din. Thus, the write current Iw flows in one direction of the two directions through the write wiring serving as a connection point between the first transistor 206, the second transistor 216 and the MTJ element 207, and the write operation is performed. For example, in FIG. 3, the second bit line 205 is set to the power supply voltage, and the first bit line 204 is set to the ground voltage. Therefore, the write current Iw flows in the direction from the second bit line 205 to the first bit line 204.
With reference to FIG. 4, in the read operation of the memory cell 202, the word line 203 is activated to turn on the first transistor 206 and the second transistor 216. Then, both of the second bit line 205 and the first bit line 204 are grounded. Thus, the read current Iw flows from the sense amplifier 208 through the MTJ element 207 in the memory cell 202. The sense amplifier 208 compares the read current Iw and the reference current and outputs the comparison result as the read data Qout.
The merit of the memory cell 202 lies in that the selection property of the memory cell 202 in the write operation is dramatically improved and the write operation margin is wide. Thus, the accurate control of the current value of the write current becomes unnecessary, which makes the write circuit simple and further makes the high speed write operation easy.
In the MRAM described in Japanese Patent Application Publication (JP-P2004-220759A), the series connection terminal voltage of the two MTJ elements J0 and J1 in which the complementary data are stored is read, so that the high speed read operation can be expected. However, the write operation is similar to the conventional MRAM. In particular, the write margin is narrow. Thus, the write current Iw must be accurately controlled. In short, the operational speed of the write operation is not improved. Also, in order to write the complementary data to the two MTJ elements J0 and J1, a device on the circuit is required.
On the other hand, in the MRAM described in Japanese Patent Application Publication (JP-P2004-348934A), the write current Iw is sent into the selection memory cell 202 by the transistors 206 and 216 provided inside the memory cell 202. Therefore, the operational margin is wide. Thus, the write current Iw is not required to be accurately controlled, which can attain the high speed write operation. However, since the read method similar to the conventional MRAM is performed, the margin of the read operation (the read signal) is not improved. In short, the operational speed of the read operation is not improved.
In relation to this application, Japanese Patent Application Publication (JP-P2003-249072A) discloses an MRAM having the structure in which a plurality of MTJ elements connected in series are stacked in a direction vertical to a substrate. According to such a structure, the MTJ elements can be integrated at a high density.
Also, Japanese Patent Application Publication (JP-P2005-236177A) discloses a technique for mirror-symmetrically arranging the memory arrays with respect to the axis parallel to the magnetization difficulty axis of the memory cell. According to such an arrangement, a relation between the direction of the write current flowing through the bit line and the write data is same over all of the memory cells. Thus, it is possible to keep the uniformity between the write data and the read data.
Moreover, Japanese Patent Application Publication (JP-P2004-145952A) discloses an MRAM that contains a main word line, a sub word line, a main bit line and a sub bit line. In the MRAM, an MRAM cell including an MTJ element is arranged at an intersection of the sub word line and the sub bit line. A selection transistor for selecting the sub word line is arranged on the downward side of the write current as compared with the MRAM cell and directly connected to the main word line and the sub bit line. The selection transistor is driven to involve a snack-back phenomenon. The write operation into the memory cell is performed by a substrate current of the selection transistor. According to such a configuration, the write current is not limited by the channel current of the selection transistor. In the MRAM, the substrate current is used to send the write current. Thus, the great write current can be sent through the selection transistor of the small size, thereby making the area of the memory array small.